-- Последовательный перемножитель на пять входов

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MULTIPLY_8x8_x5 is port(
	RESET : in  std_logic;							-- Сигнал сброса
	CLK   : in  std_logic;							-- Сигнал тактирования
	CLR   : in  std_logic;							-- Фронт начала перемножения
	
	DINA0 : in  std_logic_vector(7 downto 0);		-- 
	DINA1 : in  std_logic_vector(7 downto 0);		--
	DINA2 : in  std_logic_vector(7 downto 0);		-- Входы A
	DINA3 : in  std_logic_vector(7 downto 0);		--
	DINA4 : in  std_logic_vector(7 downto 0);		--
	
	DINB0 : in  std_logic_vector(7 downto 0);		--
	DINB1 : in  std_logic_vector(7 downto 0);		--
	DINB2 : in  std_logic_vector(7 downto 0);		-- Входы B
	DINB3 : in  std_logic_vector(7 downto 0);		--
	DINB4 : in  std_logic_vector(7 downto 0);		--
	
	DOUT0 : out std_logic_vector(15 downto 0);		--
	DOUT1 : out std_logic_vector(15 downto 0);		--
	DOUT2 : out std_logic_vector(15 downto 0);		-- Выходы
	DOUT3 : out std_logic_vector(15 downto 0);		--
	DOUT4 : out std_logic_vector(15 downto 0)		--
);
end MULTIPLY_8x8_x5;

architecture RTL of MULTIPLY_8x8_x5 is

--Сигналы для подключения перемножителя
signal A : std_logic_vector(7 downto 0);
signal B : std_logic_vector(7 downto 0);
signal C : std_logic_vector(15 downto 0);

-- Счетчик тактов
signal CNTR : std_logic_vector(5 downto 0);

-- Зажержанный на один такт сигнал  CLR
signal CLR_Z    : std_logic;

--Сигналы для выбора входов/выхода
signal DA01 : std_logic_vector(7 downto 0);
signal DA02 : std_logic_vector(7 downto 0);
signal DA1  : std_logic_vector(7 downto 0);
signal DB01 : std_logic_vector(7 downto 0);
signal DB02 : std_logic_vector(7 downto 0);
signal DB1  : std_logic_vector(7 downto 0);

component MULTIPLY_8x8 is port(
	DINA : in  std_logic_vector(7 downto 0);
	DINB : in  std_logic_vector(7 downto 0);
	DOUT : out std_logic_vector(15 downto 0));
end component;

begin

	process(RESET, CLK, CLR)
	begin
		if RESET = '1' then
			CLR_Z <= '0';
		elsif Rising_edge(CLK) then
			if (CLR = '1') then
				CLR_Z <= '1';
			else
				CLR_Z <= '0';
			end if;
		end if;
	end process;


	process(RESET, CLK, CLR, CLR_Z)
	begin
		if RESET = '1' then
			CNTR <= "000000";
		elsif Falling_edge(CLK) then
			if CLR = '1' and CLR_Z = '0' then
				CNTR <= "000000";
			else 
				CNTR <= CNTR + '1';
			end if;
		end if;
	end process;

	process(CNTR)
	begin
		if CNTR = "000000" then
			A <= DINA0;
			B <= DINB0;
		elsif CNTR = "000001" then
			A <= DINA1;
			B <= DINB1;
		elsif CNTR = "000010" then
			A <= DINA2;
			B <= DINB2;
		elsif CNTR = "000011" then
			A <= DINA3;
			B <= DINB3;
		elsif CNTR = "000100" then
			A <= DINA4;
			B <= DINB4;
		end if;
	end process;
	
	DOUT0 <= C when CNTR = "000000";
	DOUT1 <= C when CNTR = "000001";
	DOUT2 <= C when CNTR = "000010";
	DOUT3 <= C when CNTR = "000011";
	DOUT4 <= C when CNTR = "000100";

MUL_8x8_inst : MULTIPLY_8x8 port map(
	DINA => A,
	DINB => B,
	DOUT => C);

end RTL;